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A low-power three-stage amplifier for driving large capacitive load is proposed. The feedback path formed by the active-feedback Miller capacitor leads to a high frequency complex-pole but a high Q-value, which significantly deteriorates the stability of the amplifier. The serial RC stage introduced as the second stage output load can optimize the resistor Rz and the capacitor Cz under fixed power and small compensation capacitor Ca, which brings about a suitable Q-value of the complex-pole and the gain-bandwidth product extension of the amplifier. The amplifiers were designed and implemented in a standard 65 nm CMOS process with capacitive loads of 500 p F and 2 n F, respectively. The post-layout simulation results show that the amplifier driving the 500 p F capacitive load can achieve a gain of 113 d B, a phase margin of 50.6° and a gain-bandwidth product of 5.22 MHz while consuming 24 μW from a 1.2 V supply. For the 2 n F capacitive load, the amplifier has a gain of 102 d B, a phase margin of 52.8°, a gain-bandwidth product of 4.41 MHz and a power of 43 μW. The total compensation capacitors are equal to 1.13 p F and 1.03 p F. The better figures-of-merits are 108 750 and 205 113(MHz×p F/m W). The layout areas are 0.064 mm×0.026 mm and 0.063 mm×0.027 mm. Compared with the CFCC scheme, the gainbandwidth product is extended by 1.6 times at CL=500 p F and Ca=1.1 p F. 相似文献
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A low cost of die area and power consumption CMOS image sensor readout circuit with fixed pattern noise(FPN) cancellation is proposed.By using only one coupling capacitor and switch in the double FPN cancelling correlative double sampling(CDS),pixel FPN is cancelled and column FPN is stored and eliminated by the sampleand-hold operation of digitally programmable gain amplifier(DPGA).The bandwidth balance technology based on operational amplifier(op-amp) sharing is also introduced to decrease the power dissipation of traditional multi-stage switched capacitor DPGA.The circuit is designed and simulated using 1P6M 0.18 μm 1.8 V/3.3 V process.Simulation results indicate that the proposed CDS scheme can achieve an FPN of less than 1 mV.The total sampling capacitor per column is 0.9 pF and no column-wise power is dissipated.The die area and FPN value are cut by 70% and 41% respectively compared with amplifier-based CDS.The op-amp sharing gain stage can achieve a 12-bit precision and also implement an 8-bit gain controlling within a gain range of 24 dB.Its power consumption is 1.4 mW,which is reduced by 57% compared with traditional schemes.The proposed readout circuit is suitable for the application of low power cost-sensitive imaging systems. 相似文献
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