A front-end automation tool supporting design,verification and reuse of SOC |
| |
| Authors: | YAN Xiao-lang YU Long-li WANG Jie-bing |
| |
| Institution: | (1) Institute of VLSI Design, Zhejiang University, 310027 Hangzhou, China;(2) C-Sky Microsystems, 310032 Hangzhou, China |
| |
| Abstract: | This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the Verilog code by more than a factor of 5, increase the efficiency of the front-end design, reduce the bug rate significantly. This tool can be used to enhance the reusability of an intellectual property model, and facilitate porting design for different platforms. |
| |
| Keywords: | System-On-Chip Verilog HDL Verification Reuse |
| 本文献已被 万方数据 SpringerLink 等数据库收录！ |
|
