Noise and linearity optimization methods for a 1.9GHz low noise amplifier |
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| Authors: | Email author" target="_blank">Guo?Wei?Email author Huang?Da-quan |
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| Institution: | (1) Department of Information and Electronic Engineering, Zhejiang University, 310027 Hangzhou, China |
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| Abstract: | Noise and linearity performances are critical characteristics for radio frequency integrated circuits (RFICs), especially
for low noise amplifiers (LNAs). In this paper, a detailed analysis of noise and linearity for the cascode architecture, a
widely used circuit structure in LNA designs, is presented. The noise and the linearity improvement techniques for cascode
structures are also developed and have been proven by computer simulating experiments. Theoretical analysis and simulation
results showed that, for cascode structure LNAs, the first metallic oxide semiconductor field effect transistor (MOSFET) dominates
the noise performance of the LNA, while the second MOSFET contributes more to the linearity. A conclusion is thus obtained
that the first and second MOSFET of the LNA can be designed to optimize the noise performance and the linearity performance
separately, without trade-offs. The 1.9GHz Complementary Metal-Oxide-Semiconductor (CMOS) LNA simulation results are also
given as an application of the developed theory. |
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| Keywords: | RFIC CMOS LNA NF noise IP3 linearity |
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