| 一种高速多通道UART芯片设计 |
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| 引用本文： | 魏代德,杨荃.一种高速多通道UART芯片设计[J].大众科技,2014(8):8-10. |
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| 作者姓名： | 魏代德 杨荃 |
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| 作者单位： | 电子科技大学电子工程学院; |
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| 摘 要： | 文章介绍了一种高速多通道通用异步接收器∕发送器（UART）的设计。在异步通信原理的基础上，设计是模块化的，且具备兼容性和灵活可配置等优点。针对CPU与UART 接口时钟频率不一致，加入了异步FIFO设计，同时引入中断机制及DMA操作模式，提高了处理器和UART 接口的效率；并且采用有理数分频器设计，扩宽了波特率的范围。在Synopsys公司系列EDA平台下通过软件仿真和FPGA验证了设计的正确性和可行性。
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| 关 键 词： | 有理数分频 串行通信 低功耗 |
Design of high-speed and multi-channel UART chip |
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| Abstract: | This paper focus on a design of a high-speed universal asynchronous receiver and transmitter （UART） . On the basis of asynchronous communication theory, the design is modularized, compatible and configurable. Dealing with the mismatch of speed between the CPU and UART, the chip applies synchronous FIFO, and also the interrupt mechanism and DMA mode, which improve the efficiency of the ports of the CPU;in addition, the chip use the design of rational number frequency division, which broaden the range of baud rate. The correctness and feasibility was conformed with the software simulation and FPGA on the EDA platform provided by Synopsys. |
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| Keywords: | FIFO DMA Rational frequency division serial communication FIFO DMA low power |
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