Parallel processing architecture of H.264 adaptive deblocking filters |
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| Authors: | Hu Wei Tao Lin Zheng-hui Lin |
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| Institution: | (1) Department of Electronic Engineering, Shanghai Jiao Tong University, Shanghai, 200240, China |
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| Abstract: | In H.264, computational complexity and memory access of deblocking filters are variable, dependent on video contents. This
paper proposes a VLSI architecture of deblocking filters with adaptive dynamic power, which avoids redundant computations
and memory accesses by precluding the blocks that can be skipped. The vertical and horizontal edges are simultaneously processed
in an advanced scan order to speed up the decoder. As a result, dynamic power of the proposed architecture can be reduced
adaptively (up to about 89%) for different videos, and the off-chip memory access is improved when compared to previous designs.
Moreover, the processing capability of the proposed architecture is in particular appropriate for real-time deblocking of
high-definition television (HDTV, 1920×1080 pixels/frame, 60 frames/s video signals) video operation at 62 MHz. Using the
proposed architecture, power can be reduced by up to about 89% and processing time by from 25% to 81% compared with previous
designs.
Project (No. NSS’ USA5978) supported by the National Science Foundation of the United States under the East Asia Pacific Program |
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| Keywords: | Deblocking filter Adaptive dynamic power Parallel processing Pipeline H 264 |
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