| 星载SAR方位压缩处理的FPGA实现 |
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| 作者姓名： | 郑晓双 禹卫东 |
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| 作者单位： | 1.中国科学院电子学研究所 北京 100080；
2中国科学院研究生院 北京 100049 |
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| 摘 要： | 星上实时成像处理器是未来星载合成孔径雷达的重要组成部分，它可以进一步提高星载合成孔径雷达的性能，拓宽其应用。方位压缩处理是实时成像处理的核心。本文介绍了合成孔径雷达方位压缩处理的基本原理，并对星上实时成像处理器的系统参数进行了详细分析，提出了一种基于FPGA实现星载合成孔径雷达实时成像处理器中方位压缩处理的方法，完成了包括ISA接口、FFT运算、匹配滤波和复数取模在内的方位压缩处理器的设计。根据星上环境对器件的特殊要求，选用Xilinx的VirtexII系列FPGA进行硬件实现。对点目标仿真数据和实际数据的测试表明，该方法完全满足星上实时处理需求。
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| 关 键 词： | 合成孔径雷达 实时成像处理器 现场可编程门阵列 |
Azimuth Compression of Space-Borne SAR Based on FPGAs |
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| Authors: | ZHENG Xiao-Shuang YU Wei-Dong |
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| Institution: | 1.The institute of Electronics, Chinese Academy of Sciences, Beijing 100080, China；
2Graduate School of the Chinese Academy of Sciences, Beijing 100049, China |
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| Abstract: | Real-time Imager is essential for intending space-borne Synthetic Aperture Radar (SAR). A space-borne SAR with a real-time imager integrated in it has augmented performance and broadened applications. Azimuth compression is a key in real-time imaging. This paper explains the rationale of azimuth compression of SAR and analyzes the parameters of the real-time imager in detail, then puts forward a method of azimuth compression based on FPGAs, which is used in real-time imager in space-borne SAR. Such a processor for azimuth compression concerns ISA interface, FFT operating, match filtering and absolute value computing. Considering the special demands of devices used in space environment, Xilinx VirtexII FPGAs are selected as main devices for this design. The simulation of point target and result of raw data imaging demonstrate that this method meets the requirements of real time processing in space-borne SAR. |
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| Keywords: | Synthetic Aperture Radar (SAR) Real-time Imager Field Programmable Gate Array (FPGA) |
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