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Area-time associated test cost model for SoC and lower bound of test time |
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| Authors: | ZHANG Jin-yi WENG Han-yi HUANG Xu-hui CAI Wan-lin |
| Institution: | 1. 1. Key Laboratory of Specialty Fiber Optics and Optical Access Networks, School of Communication and Information Engineering, Shanghai University, Shanghai 200072, P. R. China;Key Laboratory of Advanced Displays and System Application, School of Communication and Information Engineering,Shanghai University, Shanghai 200072, P. R. China;Microelectronic Research and Development Center, Shanghai University, Shanghai 200072, P. R. China 2. Key Laboratory of Specialty Fiber Optics and Optical Access Networks, School of Communication and Information Engineering, Shanghai University, Shanghai 200072, P. R. China;Key Laboratory of Advanced Displays and System Application, School of Communication and Information Engineering,Shanghai University, Shanghai 200072, P. R. China 3. Key Laboratory of Specialty Fiber Optics and Optical Access Networks, School of Communication and Information Engineering, Shanghai University, Shanghai 200072, P. R. China; Microelectronic Research and Development Center, Shanghai University, Shanghai 200072,P.R.China |
| Abstract: | A novel test access mechanism (TAM) architecture with multi test-channel (TC) based on IEEE Standard 1500 is proposed instead of the traditional sub-TAM structure. The cost model of an area-time associated test and the corresponding lower bound of system-on-chip (SoC) test time are established based on this TAM architecture. The model provides a more reliable method to control the SoC scheduling and reduces the complexity in related algorithm research. The result based on the area time associated test cost model has been validated using the ITC’02 test benchmark. |
| Keywords: | system-on-chip design for testability (SoC DfT) test cost test time lower bound |
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