| 一种低噪声低失调电容读出电路 |
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| 作者姓名： | 吴其松 杨海钢 张翀 尹韬 |
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| 作者单位： | 1. 中国科学院电子学研究所,北京 10019
2. 中国科学院研究生院,北京 100049 |
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| 基金项目： | 国家高技术研究发展计划项目(2007AA04Z349)资助 |
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| 摘 要： | 针对差分式电容传感器,提出了一种结构简单的低噪声、低失调电容读出电路.该电路由2相非交叠时钟控制,且对电路的寄生电容不敏感,可直接将传感器电容的变化量转化为电压信号输出.相关双采样(CDS, correlated double sampling)技术有效降低了电路的低频噪声和失调电压的影响,提高了读出电路的分辨率和动态范围.读出电路在0.35μm 2P4M标准CMOS工艺下设计流片,芯片面积为0.7mm×1.8mm,5V电源电压.电路工作在1MHz的时钟频率下,实现了0.4aF/√Hz的电容分辨率和118dB的动态范围.
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| 关 键 词： | 电容传感器 电容读出电路 相关双采样 |
| 收稿时间： | 2009-04-13 |
| 修稿时间： | 2009-05-04 |
A low-noise and low-offset capacitive readout circuit |
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| Authors: | WU Qi-Song YANG Hai-Gang ZHANG Chong Yin Tao |
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| Institution: | 1. Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China;
2. Graduate University of the Chinese Academy of Sciences, Beijing 100049, China |
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| Abstract: | This paper presents a novel structure of capacitive readout circuit for fully differential capacitive sensor. The operation of this circuit is controlled by a nonoverlapping two-phase clock. This circuit is not sensitive to parasitic capacitor. Using correlated double sampling(CDS), the low-frequency noise and voltage offset have been suppressed, so that the resolution and dynamic range of the circuit have been improved. The experiment chip has been fabricated in the standard 0.35μm CMOS process, with a single 5V power supply, and the die size is 0.7mm×1.8mm. The results show that the readout circuit achieves a resolution of 0.4aF/√Hz with 118dB dynamic range under 1MHz sampling frequency. |
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| Keywords: | capacitive sensor capacitive readout circuit CDS |
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