| 基于FPGA的10 Gbit/s伪随机序列测试装置 |
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| 引用本文： | 苗澎,王志功.基于FPGA的10 Gbit/s伪随机序列测试装置[J].东南大学学报,2007,23(4):516-519. |
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| 作者姓名： | 苗澎 王志功 |
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| 作者单位： | 东南大学射频与光电集成电路研究所 南京210096 |
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| 摘 要： | 介绍了一种基于FPGA的可编程SONET OC-192 10 Gbit/s伪随机序列发生器和比特间插入奇偶校验码BIP-8的误码测试仪.该误码测试仪为并行反馈结构,可生成PRBS序列长度为27-1,210-1,215-1,223-1和231-1,通过SFI-4接口,采用10 Gbit/s收发一体光模块,其工作速率可达10 Gbit/s.在OC-192帧同步调整电路中,采用STM-64/OC192二分查找法的帧同步法,显著提高了帧同步速度并减少了帧同步逻辑的复杂度.该系统可作为一种低成本的测试仪评估OC-192-设备与器件,以取代昂贵的商用PRBS测试仪.
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| 关 键 词： | 比特间插误码 同步数字体系 成帧器 现场可编程逻辑阵列 伪随机序列 |
| 收稿时间： | 2006-12-27 |
| 修稿时间： | 2006年12月27 |
10 Gbit/s PRBS tester implemented in FPGA |
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| Miao Peng,Wang Zhigong.10 Gbit/s PRBS tester implemented in FPGA[J].Journal of Southeast University(English Edition),2007,23(4):516-519. |
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| Authors: | Miao Peng Wang Zhigong |
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| Abstract: | The design of an FPGA(field programmable gate array) based programmable SONET (synchronous optical network) OC-192 10 Gbit/s PRBS (pseudo-random binary sequence) generator and a bit interleaved polarity 8 (BIP-8) error detector is presented.Implemented in a parallel feedback configuration,this tester features PRBS generation of sequences with bit lengths of 27-1,210-1,215-1,223-1and 231-1 for up to 10 Gbit/s applications with a 10 Gbit/s optical transceiver,via the SFI-4 (OC-192 serdes-framer interface).In the OC-192 frame alignment circuit,a dichotomy search algorithm logic which performs the functions of word alignment and STM-64/OC192 de-frame speeds up the frame sync logic and reduces circuit complexity greatly.The system can be used as a low cost tester to evaluate the performance of OC-192 devices and components,taking the replacement of precious commercial PRBS testers. |
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| Keywords: | bit interleaved polarity 8 (BIP-8) synchronous digital hierarchy (SDH) framer field programmable gate array (FPGA) pseudo-random binary sequence (PRBS) |
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