| A front-end automation tool supporting design, verification and reuse of SOC |
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| 作者姓名： | 严晓浪 余龙理 王界兵 |
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| 作者单位： | Institute of VLSI Design，Zhejiang University，Hangzhou 310027，China，Institute of VLSI Design，Zhejiang University，Hangzhou 310027，China，C-Sky Microsystems，Hangzhou 310032，China |
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| 摘 要： | This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the Verilog code by more than a factor of 5, increase the efficiency of the front-end design, reduce the bug rate significantly. This tool can be used to enhance the reusability of an intellectual property model, and facilitate porting design for different platforms.
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A front-end automation tool supporting design, verification and reuse of SOC |
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| YAN Xiao-lang,YU Long-li,WANG Jie-bing.A front-end automation tool supporting design, verification and reuse of SOC[J].Journal of Zhejiang University Science,2004(9). |
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| Authors: | YAN Xiao-lang YU Long-li WANG Jie-bing |
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| Abstract: | This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the Verilog code by more than a factor of 5, increase the efficiency of the front-end design, reduce the bug rate significantly. This tool can be used to enhance the reusability of an intellectual property model, and facilitate porting design for different platforms. |
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| Keywords: | System-On-Chip Verilog HDL Verification Reuse |
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