| VHDL描述的直接数字信号合成器的设计 |
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| 引用本文： | 王鹏,孙加存.VHDL描述的直接数字信号合成器的设计[J].苏州市职业大学学报,2009,20(4):15-18. |
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| 作者姓名： | 王鹏 孙加存 |
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| 作者单位： | 苏州市职业大学,电子信息工程系,江苏,苏州,215104 |
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| 摘 要： | 介绍了基于VHDL语言描述的直接数字信号合成器的研制．该设计采用DDS的原理，通过vHDL语言进行硬件电路的描述，插入分频电路、相位累加电路可以很好地实现高频、低频信号的产生．通过软件仿真与硬件测试，效果理想，具有一定的实用价值．
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| 关 键 词： | VHDL DDS 相位累加 分频 |
Design of Digital Signal Synthesizer Base on VHDL |
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| WANG Peng,SUN Jia-cun.Design of Digital Signal Synthesizer Base on VHDL[J].Journal of Suzhou Vocational University,2009,20(4):15-18. |
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| Authors: | WANG Peng SUN Jia-cun |
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| Institution: | (Department of Electronic Information Engineering, Suzhou Vocational University, Suzhou 215104, China) |
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| Abstract: | It introduced the design of Direct Digital Synthesizer based on VHDL. The design described the hardware circuit through VHDL and adopts the principle of DDS. The frequency division circuit and the phase addition circuit were inserted. The effect through software emulator and hardware testing is perfect and the design has some practical value. |
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| Keywords: | VHDL DDS |
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