| 基于FPGA的高速浮点FFT/IFFT处理器设计与实现 |
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| 作者姓名： | 苏斌 刘畅 潘志刚 |
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| 作者单位： | 1. 中国科学院电子学研究所, 北京 100190;
2. 中国科学院大学, 北京 100049 |
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| 基金项目： | 国家自然科学基金(61100201)资助 |
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| 摘 要： | 设计一种基于FPGA的改进的并行FFT/IFFT蝶形运算结构.该结构采用按时间抽选的FFT基-2蝶形算法对IEEE单精度浮点数构成的复数进行8路并行处理.利用Xilinx ISE 13.1软件完成FFT/IFFT处理器的设计, 并在Virtex6硬件平台上进行验证.结果表明, 利用这种8路并行结构设计的FFT/IFFT处理器可在合理利用硬件资源的同时提高运算速度及精度.
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| 关 键 词： | FPGA 单精度浮点 FFT/IFFT 基-2蝶形算法 并行结构 |
| 收稿时间： | 2014-03-06 |
| 修稿时间： | 2014-05-12 |
Design and implementation of high-speed floating points FFT processor based on FPGA |
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| Authors: | SU Bin LIU Chang PAN Zhigang |
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| Institution: | 1. Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China;
2. University of Chinese Academy of Sciences, Beijing 100049, China |
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| Abstract: | An improved parallel FFT/IFFT butterfly structure is presented. The structure, which is based on the decimation-in-time (DIT) Radix-2 algorithm, contains 8 paths in parallel. IEEE single precision floating complex FFT/IFFT processors are designed by using this parallel structure and achieved with Xilinx ISE 13.1 software. Verifications are carried out with Virtex6 FPGA of Xilinx. The results show that the FFT/IFFT processors can make use of the resources reasonably and enhance both the speed and precision of computation. |
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| Keywords: | FPGA single precision floating FFT/IFFT Radix-2 algorithm parallel structure |
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