| 2.5GHz CMOS高速双模前置分频器设计 |
| |
| 引用本文： | 杨文荣,曹家麟,冉峰,王键.2.5GHz CMOS高速双模前置分频器设计[J].上海大学学报(英文版),2004,8(3). |
| |
| 作者姓名： | 杨文荣 曹家麟 冉峰 王键 |
| |
| 摘 要： |
|
A High-Speed Dual Modulus Prescaler Using 0.25μm CMOS Technology |
| |
| YANG Wen-rong,CAO Jia-lin,RAN Feng,WANG Jian.A High-Speed Dual Modulus Prescaler Using 0.25μm CMOS Technology[J].Journal of Shanghai University(English Edition),2004,8(3). |
| |
| Authors: | YANG Wen-rong CAO Jia-lin RAN Feng WANG Jian |
| |
| Abstract: | A high-speed dual-modulus divide-by-32/33 prescaler has been developed using 0.25 μm CMOS technology. The source-coupled logic (SCL) structure is used to reduce the switching noise and to ameliorate the power-speed tradeoff. The proposed prescaler can operate at high frequency with a low-power consumption. Based on the 2.5 V, 0.25 μm CMOS model, simulation results indicate that the maximum input frequency of the prescaler is up to 3. 2 GHz. Running at 2. 5 V, the circuit consumes only 4.6 mA at an input frequency 2.5 GHz. |
| |
| Keywords: | CMOS prescaler source-coupled logic(SCL) phase-locked loop(PLL) |
| 本文献已被 万方数据 等数据库收录！ |
|
